1. Field
Example embodiments relate to a stack package and a method of manufacturing the stack package. More particularly, example embodiments relate to a stack package including a plurality of stacked semiconductor chips and a method of manufacturing the stack package.
2. Description of the Related Art
Semiconductor packages are becoming miniaturized and lightweight according to the miniaturization trend of electronic products using semiconductor devices. For example, memory devices, e.g., dynamic random access memory (DRAM) or flash memory, may be mounted in a chip scale package of the semiconductor package. The chip scale package may be broadly applicable to miniaturized and mobile products.
On the other hand, in order to ensure reliability and price competitiveness of the chip scale package, a stack package including stacked semiconductor chips on a wafer level has been researched.
The wafer level stack package may include a mounting substrate and semiconductor chips stacked on the mounting substrate. For example, the stacked semiconductor chips may be electrically connected to one another by a through electrode that penetrates the semiconductor chip. A conductive connection member, e.g., bonding wire, may electrically connect the semiconductor chips to a bonding pad that may be connected to a circuit pattern formed on the mounting substrate.
However, in order to form the circuit pattern on the mounting substrate, an electroplating process may be performed using a relatively long plating wiring. This relatively long plating wiring may increase a capacitance and be an obstacle to high operating speed of a stack package.